It is frequently desired to read and write data from dynamic random access memories (DRAM) integrated circuits (ICs). As the amount of data stored in each memory IC increases, and as clock frequencies increase for devices exchanging data with memory ICs increases, there is increasing need to be able to read data out of the memory ICs with progressively higher bandwidth. This need is not easily met.
Previous generations of DRAM devices have included fast page mode DRAM and extended data output (EDO) DRAM. These DRAMs capture input data and drive output data at the falling edge of a column address strobe* (CAS*) signal, where the "*" indicates complement.
In synchronous DRAM (SDRAM), the data trigger point for read and write operations is the rising edge of the clock signal. These conventional DRAMs are referred to as single data-rate (SDR) DRAM devices. The peak bandwidth (megabytes/second) of a memory system using SDR DRAMs is given as: EQU (memory system bus width).times.(clock frequency) (Eq. 1)
Obtaining a higher peak bandwidth from a SDR DRAM system requires making the clock as fast as possible and expanding the system bus width to be as wide as possible.
However, the clock driver has to drive all DRAMs in the memory system in parallel, which requires driving a capacitive load and includes synchronization requirements. Accordingly, higher clock speeds may be difficult to achieve in practice. Additionally, increasing the bus width also requires greater area on the circuit board holding the DRAM system. As a result, it is not easy to increase the peak bandwidth of a SDR DRAM system.
Double data rate (DDR) DRAM systems are a more attractive way to get a higher data rate and thus greater system bandwidth. In DDR DRAM systems, both the rising and falling edges of the clock signal or data strobe are trigger points for read and write operations. DDR DRAM systems thus provide double the peak data rate of comparable SDR DRAM systems using the same clock frequency, but require increased timing accuracy.
A differential clock (CLK and CLK*) scheme is used in DDR DRAM memory systems to address the increased timing accuracy requirements. However, there is still a need to synchronize internal clock signals with clocking signals in the circuitry external to the DDR DRAM. Further, because transitions in these clock signals at which data are transferred occur substantially more frequently than those of CAS* signals in SDR DRAMs, the timing tolerances are much tighter. As a result, there is need to develop new approaches to generating internal clocking signals CLK and CLK* and to synchronize these clock signals as well as output data with external clocking signals XCLK.